Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
IEEE Transactions on Computers
Coping with Latency in SOC Design
IEEE Micro
GALA (Globally Asynchronous - Locally Arbitrary) Design
Concurrency and Hardware Design, Advances in Petri Nets
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Polynomial-time techniques for approximate timing analysis of asynchronous systems
Polynomial-time techniques for approximate timing analysis of asynchronous systems
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synchronous elastic circuits with early evaluation and token counterflow
Proceedings of the 44th annual Design Automation Conference
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
A general model for performance optimization of sequential systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Elastic Flow in an Application Specific Network-on-Chip
Electronic Notes in Theoretical Computer Science (ENTCS)
Performance Evaluation of Elastic GALS Interfaces and Network Fabric
Electronic Notes in Theoretical Computer Science (ENTCS)
Dataflow Architectures for GALS
Electronic Notes in Theoretical Computer Science (ENTCS)
Structural integrity: safety in miniature technology
ACM SIGBED Review - Special issue on the RTSS forum on deeply embedded real-time computing
Network Simplicity for Latency Insensitive Cores
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Synthesizing synchronous elastic flow networks
Proceedings of the conference on Design, automation and test in Europe
Transactions on Petri Nets and Other Models of Concurrency I
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Performance optimization of elastic systems using buffer resizing and buffer insertion
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Future of Formal Methods and GALS Design
Electronic Notes in Theoretical Computer Science (ENTCS)
Electronic Notes in Theoretical Computer Science (ENTCS)
Latency-Insensitive Design: Retry Relay-Station and Fusion Shell
Electronic Notes in Theoretical Computer Science (ENTCS)
Electronic Notes in Theoretical Computer Science (ENTCS)
Retiming and recycling for elastic systems with early evaluation
Proceedings of the 46th Annual Design Automation Conference
Speculation in elastic systems
Proceedings of the 46th Annual Design Automation Conference
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overscaling-friendly timing speculation architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Automatic microarchitectural pipelining
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic pipelining from transactional datapath specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
Control network generator for latency insensitive designs
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Variable-latency design by function speculation
Proceedings of the Conference on Design, Automation and Test in Europe
Research Letters in Signal Processing
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Synchronous elasticization at a reduced cost: utilizing the ultra simple fork and controller merging
Proceedings of the International Conference on Computer-Aided Design
Symbolic performance analysis of elastic systems
Proceedings of the International Conference on Computer-Aided Design
A Scheduling Strategy for Synchronous Elastic Designs
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, fine-granularity elasticity can be introduced at the level of functional units (e.g. ALUs, memories). A formal specification of the protocol is defined and an efficient scheme for the implementation of elasticity that involves no datapath overhead is presented. The opportunities this protocol opens for microarchitectural design are discussed.