Coping with Latency in SOC Design
IEEE Micro
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
A fully-automated desynchronization flow for synchronous circuits
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synchronous elasticization at a reduced cost: utilizing the ultra simple fork and controller merging
Proceedings of the International Conference on Computer-Aided Design
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Creating latency insensitive or asynchronous designs from clocked designs has potential benefits of increased modularity and robustness to variations. Several transformations have been suggested in the literature and each of these require a handshake control network (examples include synchronous elasticization and desynchronization). Numerous implementations of the control network are possible. This paper reports on an algorithm that has been proven to generate an optimal control network consisting of the minimum number of 2-input join and 2-output fork control components. This can substantially reduce the area and power consumption of a system. The algorithm has been implemented in a CAD tool, called CNG. It has been applied to the MiniMIPS processor showing a 14% reduction in the number of control steering units over a hand optimized design in a contemporary work.