A fully-automated desynchronization flow for synchronous circuits
Proceedings of the 44th annual Design Automation Conference
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Network Simplicity for Latency Insensitive Cores
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Transactions on Petri Nets and Other Models of Concurrency I
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Enabling adaptability through elastic clocks
Proceedings of the 46th Annual Design Automation Conference
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Loosely time-triggered architectures for cyber-physical systems
Proceedings of the Conference on Design, Automation and Test in Europe
Control network generator for latency insensitive designs
Proceedings of the Conference on Design, Automation and Test in Europe
Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A unifying view of loosely time-triggered architectures
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Modeling and synthesis of asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-driven clustering of asynchronous circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Desynchronization: design for verification
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
Design of low energy, high performance synchronous and asynchronous 64-point FFT
Proceedings of the Conference on Design, Automation and Test in Europe
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
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Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture