Communications of the ACM
Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Four State Asynchronous Architectures
IEEE Transactions on Computers
VHDL (2nd ed.)
Phased logic: a design methodology for delay-insensitive, synchronous circuitry
Phased logic: a design methodology for delay-insensitive, synchronous circuitry
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Logical timing (global synchronization of asynchronous arrays)
PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
A doubly-latched asynchronous pipeline
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Generalized Early Evaluation in Self-Timed Circuits
Proceedings of the conference on Design, automation and test in Europe
From Synchronous to Asynchronous: An Automatic Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An ultra-low energy asynchronous processor for Wireless Sensor Networks
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
A fully-automated desynchronization flow for synchronous circuits
Proceedings of the 44th annual Design Automation Conference
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Early evaluation for performance enhancement in phased logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Automated synchronous-to-asynchronous circuit conversion can be considered as one area of clockless design style, which is becoming more and more interesting for synchronous designers with lack of knowledge and experience in the real asynchronous circuit design. Another reason why it is becoming so interesting is that the languages and design styles for specification of asynchronous circuits require a learning curve to understand, become proficient with them, and to use them effectively. Hence, numerous approaches for automated conversion of synchronous circuits into their asynchronous counterparts have been proposed in recent years. The main reason is the exploitation of the often claimed advantages of asynchronous circuits, especially their lower power consumption. This paper surveys some of the available well-known synchronous-to-asynchronous conversion techniques and tries to present both their positive and negative properties.