Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
Statistical results for system identification based on quantized observations
Automatica (Journal of IFAC)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power TinyOS tuned processor platform for wireless sensor network motes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
| Hi-index | 0.00 |
This paper describes the design flow used for an asynchronous 8-bit processor implementing the Atmel AVR instruction set architecture. The goal is to show dramatic reductions in power and energy with respect to the synchronous case, while retaining essentially a traditional design flow. The processor was implemented in a 130nm technology using desynchronization, starting from an initial design downloaded from OpenCores.org. It consumes 14 pJ per instruction to deliver 170 MIPS at 1.2 V, and 2.7 pJ per instruction to deliver 48 MIPS at 0.54 V. It thus dramatically improves the energy consumed per instruction with respect to previous results from the literature.