Generalized Early Evaluation in Self-Timed Circuits

Authors:
M. Thornton;K. Fazel;R. Reese;C. Traver
Affiliations:
Department of Electrical and Computer Engineering, Mississippi State University;Department of Electrical and Computer Engineering, Mississippi State University;Department of Electrical and Computer Engineering, Mississippi State University;Department of Electrical Engineering, Union College, Schenectady, New York
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

Phased logic has been proposed as a technique for realizingself-timed circuitry that is delay-insensitive and requiresno global clock signals. Early evaluation techniqueshave been applied to asynchronous circuits in the past inorder to achieve throughput increases. A general methodfor computing early evaluation functions is presented forthis design style. Experimental results are given that showthe increase in throughput of various benchmark circuits.The results show that as much as a 30% speedup can beachieved in some cases.