Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Enabling adaptability through elastic clocks
Proceedings of the 46th Annual Design Automation Conference
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VariPipe: low-overhead variable-clock synchronous pipelines
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Control network generator for latency insensitive designs
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and synthesis of asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Variability is one of the fundamental problems faced by nano-scale electronic circuits and is expected to become even worse as process technology scales. Desynchronization is a design methodology, which converts a synchronous gate-level circuit into a more robust asynchronous one. In this paper, we describe the first fully-automated desynchronization design flow, based only on contemporary synchronous EDA tools and a new point tool for performing the desynchronization transformation. The flow was used to implement, down to mask layout level, a simple pipelined processor in a 90nm industrial library. We show that the desynchronization methodology can be easily integrated into contemporary industrial EDA flows. Results, on the design implemented, indicate that desynchronized circuits exhibit increased variability tolerance and better average case performance, for a small area and power overhead.