Quantitative system performance: computer system analysis using queueing network models
Quantitative system performance: computer system analysis using queueing network models
Communicating sequential processes
Communicating sequential processes
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Safety analysis of timing properties in real-time systems
IEEE Transactions on Software Engineering - Special issue on reliability and safety in real-time process control
Static Analysis of Real-Time Distributed Systems
IEEE Transactions on Software Engineering
Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Timing verification using HDTV
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Compiling Real-Time Specifications into Extended Automata
IEEE Transactions on Software Engineering - Special issue: specification and analysis of real-time systems
An approach to symbolic timing verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Stari: a technique for high-bandwidth communication
Stari: a technique for high-bandwidth communication
Representing and modeling digital circuits
Representing and modeling digital circuits
Real-time symbolic model checking for discrete time models
Theories and experiences for real-time system development
Practical applications of an efficient time separation of events algorithm
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Temporal Analysis of Time Bounded Digital Systems
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Verification of Safety Critical Systems Using TTM/RTTL
Proceedings of the Real-Time: Theory in Practice, REX Workshop
A new interface specification methodology and its application to transducer synthesis
A new interface specification methodology and its application to transducer synthesis
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Bounded Delay Timing Analysis of a Class of CSP Programs
Formal Methods in System Design
Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A model for scheduling protocol-constrained components and environments
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Probabilistic application modeling for system-level perfromance analysis
Proceedings of the conference on Design, automation and test in Europe
Timing driven co-design of networked embedded systems
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Rate analysis for embedded systems
Readings in hardware/software co-design
Reducing probabilistic timed petri nets for asynchronous architectural analysis
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Interface Design for Core-Based Systems
IEEE Design & Test
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
From max-plus algebra to nonexpansive mappings: a nonlinear theory for discrete event systems
Theoretical Computer Science
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Symbolic Time Separation of Events
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
Proceedings of the 41st annual Design Automation Conference
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Min-Max Inequalities and the Timing Verification Problem with Max and Linear Constraints
Discrete Event Dynamic Systems
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-level performance/power analysis for platform-based design of multimedia applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fully-automated desynchronization flow for synchronous circuits
Proceedings of the 44th annual Design Automation Conference
Globally optimal solutions of max---min systems
Journal of Global Optimization
An efficient algorithm for time separation of events in concurrent systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Time separations of cyclic event rule systems with min-max timing constraints
Theoretical Computer Science
Performance estimation and slack matching for pipelined asynchronous architectures with choice
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Design and Tool Flow of Multimedia MPSoC Platforms
Journal of Signal Processing Systems
High performance asynchronous design flow using a novel static performance analysis method
Computers and Electrical Engineering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware and Petri nets: application to asynchronous circuit design
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
Challenges in verifying communication fabrics
ITP'11 Proceedings of the Second international conference on Interactive theorem proving
The level set method for the two-sided max-plus eigenproblem
Discrete Event Dynamic Systems
| Hi-index | 14.98 |
Determining the time separation of events is a fundamental problem in the analysis, synthesis, and optimization of concurrent systems. Applications range from logic optimization of asynchronous digital circuits to evaluation of execution times of programs for real-time systems. We present an efficient algorithm to find exact (tight) bounds on the separation time of events in an arbitrary process graph without conditional behavior. This result is more general than the methods presented in several previously published papers as it handles cyclic graphs and yields the tightest possible bounds on event separations. The algorithm is based on a functional decomposition technique that permits the implicit evaluation of an infinitely unfolded process graph. Examples are presented that demonstrate the utility and efficiency of the solution. The algorithm will form a basis for exploration of timing-constrained synthesis techniques.