Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
COSY: its relation to nets and to CSP
Advances in Petri nets 1986, part II on Petri nets: applications and relationships to other models of concurrency
Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Stubborn sets for reduced state generation
APN 90 Proceedings on Advances in Petri nets 1990
An approach to symbolic timing verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Trace algebra for automatic verification of real-time concurrent systems
Trace algebra for automatic verification of real-time concurrent systems
Minimum and maximum delay problems in real-time systems
Formal Methods in System Design - Special issue on computer-aided verification: special methods I
Representing and modeling digital circuits
Representing and modeling digital circuits
Real-time symbolic model checking for discrete time models
Theories and experiences for real-time system development
Timing analysis and verification of timed asynchronous circuits
Timing analysis and verification of timed asynchronous circuits
Optimization of linear max-plus systems with application to timing analysis
Optimization of linear max-plus systems with application to timing analysis
A general approach to performance analysis and optimization of asynchronous circuits
A general approach to performance analysis and optimization of asynchronous circuits
Practical applications of an efficient time separation of events algorithm
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Modular Construction and Partial Order Semantics of Petri Nets
Modular Construction and Partial Order Semantics of Petri Nets
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Proceedings of the 6th International Conference on Computer Aided Verification
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Coverage Preserving Reduction Strategies for Reachability Analysis
Proceedings of the IFIP TC6/WG6.1 Twelth International Symposium on Protocol Specification, Testing and Verification XII
Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Delay Analysis in Synchronous Programs
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
OR Causality: Modelling and Hardware Implementation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
Proceedings of the Real-Time: Theory in Practice, REX Workshop
CAD directions for high performance asynchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Partial Order Verification of Programmable Logic Controllers
ICATPN '01 Proceedings of the 22nd International Conference on Application and Theory of Petri Nets
Symbolic Time Separation of Events
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Time separations of cyclic event rule systems with min-max timing constraints
Theoretical Computer Science
Timing analysis of scenario-based specifications using linear programming
Software Testing, Verification & Reliability
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We describe an algebraic technique for performing timing analysis ofa class of asynchronous circuits described as CSP programs (includingMartin‘s probe operator) with the restrictions that there is no OR-causalityand that guard selection is either completely free or mutually exclusive.Such a description is transformed into a safe Petri net with interval timedelays specified on the places of the net. The timing analysis we performdetermines the extreme separation in time between two communication actionsof the CSP program for all possible timed executions of the system. Weformally define this problem, propose an algorithm for its solution, anddemonstrate polynomial running time on a non-trivial parameterized example.Petri nets with 3000 nodes and 10^16 reachable states have beenanalyzed using these techniques.