Efficient partial enumeration for timing analysis of asynchronous systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of asynchronous circuits using time Petri net unfolding
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Timing analysis for synthesis in microprocessor interface design
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Bounded Delay Timing Analysis of a Class of CSP Programs
Formal Methods in System Design
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Deriving Petri Nets from Finite Transition Systems
IEEE Transactions on Computers
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
AMAST '98 Proceedings of the 7th International Conference on Algebraic Methodology and Software Technology
Efficient Guiding Towards Cost-Optimality in UPPAAL
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Partial Order Path Technique for Checking Parallel Timed Automata
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
Timed Verification of Asynchronous Circuits
Concurrency and Hardware Design, Advances in Petri Nets
As Cheap as Possible: Efficient Cost-Optimal Reachability for Priced Timed Automata
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
Nordic Journal of Computing
Technology mapping of timed circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Verification of Delayed-Reset Domino Circuits Using ATACS
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Verification system for real-time specification based on extended real-time logic
RTCSA '95 Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications
A quadratic-time DBM-based successor algorithm for checking timed automata
Information Processing Letters
State space computation and analysis of Time Petri Nets
Theory and Practice of Logic Programming
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
A quadratic-time DBM-based successor algorithm for checking timed automata
Information Processing Letters
Model checking bounded prioritized time Petri nets
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
HSCC'05 Proceedings of the 8th international conference on Hybrid Systems: computation and control
On interleaving in timed automata
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
| Hi-index | 0.01 |