Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Techniques for automatic verification of real-time systems
Techniques for automatic verification of real-time systems
Trace algebra for automatic verification of real-time concurrent systems
Trace algebra for automatic verification of real-time concurrent systems
Symbolic model checking for real-time systems
Information and Computation
Representing and modeling digital circuits
Representing and modeling digital circuits
Approximations for verifying timing properties
Theories and experiences for real-time system development
Efficient partial enumeration for timing analysis of asynchronous systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On the SUP-INF Method for Proving Presburger Formulas
Journal of the ACM (JACM)
An algebraic framework for urgency
Information and Computation
Guarded commands, nondeterminacy and formal derivation of programs
Communications of the ACM
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Hauptvortrag: Quantifier elimination for real closed fields by cylindrical algebraic decomposition
Proceedings of the 2nd GI Conference on Automata Theory and Formal Languages
Timing analysis of asynchronous circuits using timed automata
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic Verification of Timed Circuits
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
Lectures on Embedded Systems, European Educational Forum, School on Embedded Systems
Model-Checking for Real-Time Systems
FCT '95 Proceedings of the 10th International Symposium on Fundamentals of Computation Theory
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Verification of Timed Systems Using POSETs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Efficient Timing Analysis Algorithms for Timed State Space Exploration
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
A new polynomial-time algorithm for linear programming
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Approximate reachability analysis of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
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We describe a methodology for analyzing timed systems symbolically. Given a formula representing a set of timed states, we describe howto determine a new formula that represents the set of states reachable by taking a discrete transition or by advancing time. The symbolic representations are given as formulae expressed in a simple first-order logic over constraints of the form x-y 驴 d which can be combined with Boolean operators and existentially quantified. The main contribution is a way of advancing time symbolically essentially by quantifying out a special variable z which is used to represent the current zero point in time. We describe how to model asynchronous circuits using timed guarded commands and provide examples that demonstrate the potential of the symbolic analysis.