Symbolic model checking for real-time systems
Information and Computation
Real-time symbolic model checking for discrete time models
Theories and experiences for real-time system development
Symbolic model checking of process networks using interval diagram techniques
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic verification of real-time communicating systems by constraint-solving
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Automata For Modeling Real-Time Systems
ICALP '90 Proceedings of the 17th International Colloquium on Automata, Languages and Programming
The Bounded Retransmission Protocol Must Be on Time!
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Formal Design and Analysis of a Gear Controller
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Verification of an Audio Control Protocol
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
Verification of Real-Time Systems by Successive Over and Under Approximation
Proceedings of the 7th International Conference on Computer Aided Verification
Verification of an Audio Protocol with Bus Collision Using UPPAAL
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Data-Structures for the Verification of Timed Automata
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Formal Verification of a TDMA Protocol Start-Up Mechanism
PRFTS '97 Proceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems
Two examples of verification of multirate timed automata with Kronos
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Compositional and symbolic model-checking of real-time systems
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Approximate reachability analysis of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
A User Guide to HyTech
Region Encoding Diagram for Fully Symbolic Verification of Real-Time Systems
COMPSAC '00 24th International Computer Software and Applications Conference
STACS '03 Proceedings of the 20th Annual Symposium on Theoretical Aspects of Computer Science
Efficient Verification of Timed Automata with BDD-Like Data-Structures
VMCAI 2003 Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Timed Verification of Asynchronous Circuits
Concurrency and Hardware Design, Advances in Petri Nets
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
ICATPN '01 Proceedings of the 22nd International Conference on Application and Theory of Petri Nets
Attacking Symbolic State Explosion
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Better is Better than Well: On Efficient Verification of Infinite-State Systems
LICS '00 Proceedings of the 15th Annual IEEE Symposium on Logic in Computer Science
Model Checking and Artificial Intelligence
Improvements for the Symbolic Verification of Timed Automata
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Hierarchical Set Decision Diagrams and Regular Models
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Verifying Stateful Timed CSP Using Implicit Clocks and Zone Abstraction
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Symbolic and compositional reachability for timed automata
RP'10 Proceedings of the 4th international conference on Reachability problems
Making the right cut in model checking data-intensive timed systems
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Developing UPPAAL over 15 years
Software—Practice & Experience
PRTS: an approach for model checking probabilistic real-time hierarchical systems
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
An MTBDD-based implementation of forward reachability for probabilistic timed automata
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Adding invariants to event zone automata
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Verification, performance analysis and controller synthesis for real-time systems
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
A logic for knowledge, correctness, and real time
CLIMA'04 Proceedings of the 5th international conference on Computational Logic in Multi-Agent Systems
Symbolic model checking of finite precision timed automata
ICTAC'05 Proceedings of the Second international conference on Theoretical Aspects of Computing
SAT-based Unbounded Model Checking of Timed Automata
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
Beyond lassos: complete SMT-Based bounded model checking for timed automata
FMOODS'12/FORTE'12 Proceedings of the 14th joint IFIP WG 6.1 international conference and Proceedings of the 32nd IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
SAT-Based Reachability Checking for Timed Automata with Discrete Data
Fundamenta Informaticae - Special Issue on Concurrency Specification and Programming (CS&P)
Modeling and verifying hierarchical real-time systems using stateful timed CSP
ACM Transactions on Software Engineering and Methodology (TOSEM)
Transient analysis of networks of stochastic timed automata using stochastic state classes
QEST'13 Proceedings of the 10th international conference on Quantitative Evaluation of Systems
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One of the major problems in applying automatic verification tools to industrial-size systems is the excessive amount of memory required during the state-space exploration of a model. In the setting of real-time, this problem of state-explosion requires extra attention as information must be kept not only on the discrete control structure but also on the values of continuous clock variables. In this paper, we exploit Clock Difference Diagrams, CDD's, a BDD-like data-structure for representing and effectively manipulating certain nonconvex subsets of the Euclidean space, notably those encountered during verification of timed automata. A version of the real-time verification tool Uppaal using CDD's as a compact data-structure for storing explored symbolic states has been implemented. Our experimental results demonstrate significant spacesavings: for eight industrial examples, the savings are in average 42% with moderate increase in runtime. We further report on how the symbolic state-space exploration itself may be carried out using CDD's.