Communicating sequential processes
Communicating sequential processes
Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
Compiling Real-Time Specifications into Extended Automata
IEEE Transactions on Software Engineering - Special issue: specification and analysis of real-time systems
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
The algebra of timed processes, ATP: theory and application
Information and Computation
An operational semantics for timed CSP
Information and Computation
Time-abstracted bisimulation: implicit specifications and decidability
Information and Computation
Communications of the ACM
Automatic verification of real-time communicating systems by constraint-solving
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
A Timed Model for Communicating Sequential Processes
ICALP '86 Proceedings of the 13th International Colloquium on Automata, Languages and Programming
CCS + Time = An Interleaving Model for Real Time Systems
ICALP '91 Proceedings of the 18th International Colloquium on Automata, Languages and Programming
TACAS '95 Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Verifying Abstractions of Timed Systems
CONCUR '96 Proceedings of the 7th International Conference on Concurrency Theory
A Case Study in Timed CSP: The Railroad Crossing Problem
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Modeling Aircraft Mission Computer Task Rates
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Some Thoughts on Statecharts, 13 Years Later
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Kronos: A Model-Checking Tool for Real-Time Systems
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
TAXYS: A Tool for the Development and Verification of Real-Time Embedded Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
The Compositional Specification of Timed Systems - A Tutorial
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
On the expressive power of CSP refinement
Formal Aspects of Computing
Testing real-time embedded software using UPPAAL-TRON: an industrial case study
Proceedings of the 5th ACM international conference on Embedded software
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
IEEE Transactions on Software Engineering
PAT: Towards Flexible Verification under Fairness
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
A reasoning method for timed CSP based on constraint solving
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Analyzing hierarchical complex real-time systems
Proceedings of the eighteenth ACM SIGSOFT international symposium on Foundations of software engineering
ICOST'10 Proceedings of the Aging friendly technology for health and independence, and 8th international conference on Smart homes and health telematics
Developing model checkers using PAT
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Model checking a model checker: a code contract combined approach
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
PRTS: an approach for model checking probabilistic real-time hierarchical systems
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Towards a model checker for Nesc and wireless sensor networks
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
Symbolic model-checking of stateful timed CSP using BDD and digitization
ICFEM'12 Proceedings of the 14th international conference on Formal Engineering Methods: formal methods and software engineering
Modeling and verifying hierarchical real-time systems using stateful timed CSP
ACM Transactions on Software Engineering and Methodology (TOSEM)
Dynamic synthesis of local time requirement for service composition
Proceedings of the 2013 International Conference on Software Engineering
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In this work, we study model checking of compositional real-time systems. A system is modeled using mutable data variables as well as a compositional timed process. Instead of explicitly manipulating clock variables, a number of compositional timed behavioral patterns are used to capture quantitative timing requirements, e.g. delay, timeout, deadline, timed interrupt, etc. A fully automated abstraction technique is developed to build an abstract finite state machine from the model. The idea is to dynamically create/delete clocks, and maintain/solve a constraint on the clocks. The abstract machine weakly bi-simulates the model and, therefore, LTL model checking or trace-refinement checking are sound and complete. We enhance our home-grown PAT model checker with the technique and show its usability via the verification of benchmark systems.