Completeness in formal specification language design for process-control systems
FMSP '00 Proceedings of the third workshop on Formal methods in software practice
A Compared Study of Two Correctness Proofs for the Standardized Algorithm of ABR Conformance
Formal Methods in System Design
Formal Verification of UML Statecharts with Real-Time Extensions
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
Verification of Plan Models Using UPPAAL
FAABS '00 Proceedings of the First International Workshop on Formal Approaches to Agent-Based Systems-Revised Papers
Timed Diagnostics for Reachability Properties
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
On Memory-Block Traversal Problems in Model-Checking Timed-Systems
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
STACS '03 Proceedings of the 20th Annual Symposium on Theoretical Aspects of Computer Science
A Real-Time Animator for Hybrid Systems
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Efficient Timed Reachability Analysis Using Clock Difference Diagrams
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal Verification of a Power Controller Using the Real-Time Model Checker UPPAAL
ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems
Nordic Journal of Computing
Forward Analysis of Updatable Timed Automata
Formal Methods in System Design
Theoretical Computer Science
Compatibility Between Shared Variable Valuations in Timed Automaton Network Model-Checking
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 2 - Volume 03
Axiomatisation and decidability of multi-dimensional Duration Calculus
Information and Computation
The SAVE approach to component-based development of vehicular systems
Journal of Systems and Software
Electronic Notes in Theoretical Computer Science (ENTCS)
Improvements for the Symbolic Verification of Timed Automata
FORTE '07 Proceedings of the 27th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
Event order abstraction for parametric real-time system verification
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Model-checking Timed Temporal Logics
Electronic Notes in Theoretical Computer Science (ENTCS)
A Compositional Translation of Timed Automata with Deadlines to Uppaal Timed Automata
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Verifying Stateful Timed CSP Using Implicit Clocks and Zone Abstraction
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Weighted Timed Automata: Model-Checking and Games
Electronic Notes in Theoretical Computer Science (ENTCS)
Static guard analysis in timed automata verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Timed sequence diagrams and tool-based analysis: a case study
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
Layered composition for timed automata
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Quantitative analysis of real-time systems using priced timed automata
Communications of the ACM
Robust model-checking of timed automata via pumping in channel machines
FORMATS'11 Proceedings of the 9th international conference on Formal modeling and analysis of timed systems
Use of timed automata and model-checking to explore scenarios on ecosystem models
Environmental Modelling & Software
Efficient emptiness check for timed büchi automata
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Testing deadlock-freeness in real-time systems: a formal approach
FATES'04 Proceedings of the 4th international conference on Formal Approaches to Software Testing
FMOODS'05 Proceedings of the 7th IFIP WG 6.1 international conference on Formal Methods for Open Object-Based Distributed Systems
Efficient emptiness check for timed Büchi automata
Formal Methods in System Design
Automatic verification of real-time systems with rich data: an overview
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
An MDE-based approach to the verification of SysML state machine diagram
Proceedings of the Fourth Asia-Pacific Symposium on Internetware
Improving model checking with context modelling
Advances in Software Engineering
Specification and analysis of access control policies for mobile applications
Proceedings of the 18th ACM symposium on Access control models and technologies
Hi-index | 0.02 |
A formal and automatic verification of a real-life protocol is presented. The protocol, about 2800 lines of assembler code, has been used in products from the audio/video company Bang & Olufsen throughout more than a decade, and its purpose is to control the transmission of messages between audio/video components over a single bus. Such communications may collide, and one essential purpose of the protocol is to detect such collisions. The functioning is highly dependent on real-time considerations. Though the protocol was known to be faulty in that messages were lost occasionally, the protocol was too complicated in order for Bang & Olufsen to locate the bug using normal testing. However using the real-time verification tool UPPAAL, an error trace was automatically generated, which caused the detection of "the error" in the implementation. The error was corrected and the correction was automatically proven correct, again using UPPAAL. A future, and more automated, version of the protocol, where this error is fatal, will incorporate the correction. Hence, this work is an elegant demonstration of how model checking has had an impact on practical software development. The effort of modeling this protocol has in addition generated a number of suggestions for enriching the UPPAAL language. Hence, it's also an excellent example of the reverse impact.