Information Processing Letters
Theoretical Computer Science
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Component Software: Beyond Object-Oriented Programming
Component Software: Beyond Object-Oriented Programming
Communication and Concurrency
Time and Action Lock Freedom Properties for Timed Automata
FORTE '01 Proceedings of the IFIP TC6/WG6.1 - 21st International Conference on Formal Techniques for Networked and Distributed Systems
Validity Checking for Combinations of Theories with Equality
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
UPPAAL - Now, Next, and Future
MOVEP '00 Proceedings of the 4th Summer School on Modeling and Verification of Parallel Processes
How to Compose Presburger-Accelerations: Applications to Broadcast Protocols
FST TCS '02 Proceedings of the 22nd Conference Kanpur on Foundations of Software Technology and Theoretical Computer Science
On the Composition of Hybrid Systems
HSCC '98 Proceedings of the First International Workshop on Hybrid Systems: Computation and Control
A Comparison of Presburger Engines for EFSM Reachability
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Audio Protocol with Bus Collision Using UPPAAL
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Generating Test Cases for a Timed I/O Automaton Model
Proceedings of the IFIP TC6 12th International Workshop on Testing Communicating Systems: Method and Applications
Verifying Progress in Timed Systems
ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems
Formal Verification of a TDMA Protocol Start-Up Mechanism
PRFTS '97 Proceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
TCTL inevitability analysis of dense-time systems
CIAA'03 Proceedings of the 8th international conference on Implementation and application of automata
Toward an integratred verification environment for embedded systems
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
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A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or inconsistencies in the specification. As a result, finding out and resolving Time Action Locks is a major task for the designers of Real-time systems. Verification is one of the methods of discovering deadlocks. However, due to state explosion, the verification of deadlock freeness is computationally expensive. The aim of this paper is to present a computationally cheap testing method for Timed Automata models and pointing out any source of possible Time Action Locks to the designer. We have implemented the approach presented in the paper, which is based on the geometry of Timed Automata, via a Testing Tool called TALC (Time Action Lock Checker). TALC, which is used in the conjunction with the model checker UPPAAL, tests the UPPAAL model and provides feedback to the designer. We have illustrated our method by applying TALC to a model of a simple communication protocol.