Toward an integratred verification environment for embedded systems

Authors:
Dehui Du;Keqing He;Honghua Cao;Yutao Ma
Affiliations:
State Key Laboratory of Software Engineering, Wuhan University, Wuhan, PRC;State Key Laboratory of Software Engineering, Wuhan University, Wuhan, PRC;State Key Laboratory of Software Engineering, Wuhan University, Wuhan, PRC;State Key Laboratory of Software Engineering, Wuhan University, Wuhan, PRC
Venue:
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
Year:
2006

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Abstract

Verification development platform is a rapid, efficient and low-cost tool for embedded systems development, which helps to improve efficiency and quality of embedded software. There are some verification tools for embedded systems, however, the integrated verification environment for embedded systems is still a challenge. This paper focuses on the integrated verification environment of EUP (Embedded UML Platform), which supports functional verification of safety and liveness requirements and nonfunctional verification of time related constraints of embedded systems. The partition of functional and nonfunctional verification can facilitate the verification of different aspects of systems in different design phases. We will illustrate the feasibility of the integrated verification environment of EUP through the case study-RCS (Railway Crossing System).