Verification of embedded systems using a petri net based representation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Towards a Formal Operational Semantics of UML Statechart Diagrams
Proceedings of the IFIP TC6/WG6.1 Third International Conference on Formal Methods for Open Object-Based Distributed Systems (FMOODS)
A Framework for Translating Models and Specifications
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
ICDCS '03 Proceedings of the 23rd International Conference on Distributed Computing Systems
Eclipse Modeling Framework
Software Factories: Assembling Applications with Patterns, Models, Frameworks, and Tools
Software Factories: Assembling Applications with Patterns, Models, Frameworks, and Tools
Unifying Modeling and Simulation Based on UML Timing Diagram and UPPAAL
ICCMS '10 Proceedings of the 2010 Second International Conference on Computer Modeling and Simulation - Volume 01
Formalising UML state machines for model checking
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
Modelling and verification of web services business activity protocol
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Hi-index | 0.00 |
State Machine Diagram (SMD) is one of the SysML behavior diagrams, but it is a kind of semi-formal model language. As a consequence, models can not be verified conveniently and efficiently, especially in real-time embedded system (RTES) field as there are no descriptions of time and probability in SMD. To address these problems, we extend SMD with time and probability elements extracted from MARTE and propose a transformation algorithm based on MDE. With the algorithm, we transform the extended SMD to timed automata (TA) and then analyze and verify the transformation result using existing tools. So at the very beginning of system design, errors and deficiencies can be found. At last, we construct an instance to illustrate the validity of our approach.