Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
The algorithmic analysis of hybrid systems
Theoretical Computer Science - Special issue on hybrid systems
Formal verification of embedded systems based on CFSM networks
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic model checking of process networks using interval diagram techniques
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Intellectual property re-use in embedded system co-design: an industrial case study
Proceedings of the 11th international symposium on System synthesis
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Software Specification: A Comparison of Formal Methods
Software Specification: A Comparison of Formal Methods
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
Petri Net Analysis Using Boolean Manipulation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
CVF ¾ Coverification Framework
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
Formal verification in a component-based reuse methodology
Proceedings of the 15th international symposium on System Synthesis
ICDCS '03 Proceedings of the 23rd International Conference on Distributed Computing Systems
Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Dual Flow Nets: Modeling the control/data-flow relation in embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
State space computation and analysis of Time Petri Nets
Theory and Practice of Logic Programming
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
A Formal Approach for Analysis and Testing of Reliable Embedded Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Structural Translation from Time Petri Nets to Timed Automata
Electronic Notes in Theoretical Computer Science (ENTCS)
Compositional semantics of system-level designs written in systemC
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
Sysfier: Actor-based formal verification of SystemC
ACM Transactions on Embedded Computing Systems (TECS)
A polyadic pi-calculus approach for the formal specification of UML-RT
Advances in Software Engineering
SystemC waiting state automata
International Journal of Critical Computer-Based Systems
Formal co-verification for soc design with colored petri net
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Using simulation to test formally verified protocols in complex environments
Mathematical and Computer Modelling: An International Journal
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
An MDE-based approach to the verification of SysML state machine diagram
Proceedings of the Fourth Asia-Pacific Symposium on Internetware
Model-based requirements verification method: Conclusions from two controlled experiments
Information and Software Technology
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The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness. New verification methods that overcome the limitations of traditional techniques and, at the same time, are suitable for hardware/software systems are needed. In this work we formally define the semantics of PRES+, a Petri net based computational model aimed to represent embedded systems. We introduce an approach to formal verification of such systems: we make use of model checking to prove the correctness of embedded systems by determining the truth of CTL and TCTL formulas that specify required properties with respect to a PRES+ model. An ATM server illustrates the feasibility of our approach on practical applications.