Handbook of theoretical computer science (vol. B)
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
Verification of embedded systems using a petri net based representation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
The Temporal Semantics of Concurrent Programs
Proceedings of the International Sympoisum on Semantics of Concurrent Computation
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Modular verification of software components in C
Proceedings of the 25th International Conference on Software Engineering
Reachability Analysis for Formal Verification of SystemC
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
ICSE '81 Proceedings of the 5th international conference on Software engineering
SystemC: methodologies and applications
SystemC: methodologies and applications
Formal Semantics of Synchronous SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Modere: the model-checking engine of Rebeca
Proceedings of the 2006 ACM symposium on Applied computing
SystemC: From the Ground Up
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Modeling and Verification of Reactive Systems using Rebeca
Fundamenta Informaticae
Model-driven validation of SystemC designs
Proceedings of the 44th annual Design Automation Conference
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Improving SystemC simulation through Petri net reductions
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
On the Transformation of SystemC to AsmL Using Abstract Interpretation
Electronic Notes in Theoretical Computer Science (ENTCS)
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Compositional semantics of system-level designs written in systemC
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient symmetry reduction for an actor-based model
ICDCIT'05 Proceedings of the Second international conference on Distributed Computing and Internet Technology
Ten years of analyzing actors: Rebeca experience
Formal modeling
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
Modeling and verification of probabilistic actor systems using prebeca
ICFEM'12 Proceedings of the 14th international conference on Formal Engineering Methods: formal methods and software engineering
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SystemC is a system-level modeling language that can be used effectively for hardware/software co-design. Since a major goal of SystemC is to enable verification at higher levels of abstraction, the tendency is now directing to introducing formal verification approaches for SystemC. In this article, we propose an approach for formal verification of SystemC designs, and provide the semantics of SystemC using Labeled Transition Systems (LTS) for this purpose. An actor-based language, Rebeca, is used as an intermediate language. SystemC designs are mapped to Rebeca models and then Rebeca verification toolset is used to verify LTL and CTL properties. To tackle the state-space explosion, Rebeca model checkers offer some reduction policies that make them appropriate for SystemC verification. The approach also benefits from the modular verification and program slicing techniques applied on Rebeca models. To show the applicability of our approach, we verified a single-cycle MIPS design and two hardware/software co-designs. The results show that our approach can effectively be used both in hardware and hardware/software co-verification.