Evolving algebras 1993: Lipari guide
Specification and validation methods
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
Abstract State Machines: A Method for High-Level System Design and Analysis
Abstract State Machines: A Method for High-Level System Design and Analysis
Generating finite state machines from SystemC
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Theoretical Computer Science - Formal methods for components and objects
A framework for the functional verification of systemC models
International Journal of Parallel Programming
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The spec# programming system: an overview
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
Model-driven validation of SystemC designs
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Sysfier: Actor-based formal verification of SystemC
ACM Transactions on Embedded Computing Systems (TECS)
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
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Functional test generation for dynamic validation of current system level designs is a challenging task. Manual test writing or automated random test generation techniques are often used for such validation practices. However, directing tests to particular reachable states of a SystemC model is often difficult, especially when these models are large and complex. In this work, we present a model-driven methodology for generating directed tests that take the SystemC model under validation to specific reachable states. This allows the validation to uncover very specific scenarios which lead to different corner cases. Our formal modeling is done entirely within the Microsoft SpecExplorer tool to describe the specification of the system under validation in the notation of AsmL. We also exploit SpecExplorer's abilities for state space exploration for our test generations, and its APIs for connecting the model to implementation programs to drive the validation of SystemC models with the generated test cases.