SystemC: a modeling platform supporting multiple design abstractions
Proceedings of the 14th international symposium on Systems synthesis
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FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
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CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
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ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Formal verification of systemc designs using a petri-net based representation
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Theoretical Computer Science - Formal methods for components and objects
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Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Modeling and Verification of Reactive Systems using Rebeca
Fundamenta Informaticae
Sarir: A Rebeca to mCRL2 Translator
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Model-driven validation of SystemC designs
Proceedings of the 44th annual Design Automation Conference
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Proceedings of the 44th annual Design Automation Conference
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Spin model checker, the: primer and reference manual
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Model checking SystemC designs using timed automata
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
FMICS '09 Proceedings of the 14th International Workshop on Formal Methods for Industrial Critical Systems
Speeding Up Simulation of SystemC Using Model Checking
Formal Methods: Foundations and Applications
Process Algebra: Equational Theories of Communicating Processes
Process Algebra: Equational Theories of Communicating Processes
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Sysfier: Actor-based formal verification of SystemC
ACM Transactions on Embedded Computing Systems (TECS)
An approach for the verification of systemc designs using asml
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using Model Checking to Analyze the System Behavior of the LHC Production Grid
CCGRID '12 Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
Using model checking to analyze the system behavior of the LHC production grid
Future Generation Computer Systems
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SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC designs by providing a mapping to the process algebra mCRL2. Our mapping formalizes both the simulation semantics as well as exhaustive state-space exploration of SystemC designs. By exploiting the existing reduction techniques of mCRL2 and also its model-checking tools, we efficiently locate the race conditions in a system and resolve them. A tool is implemented to automatically perform the proposed mapping. This mapping and the implemented tool enabled us to exploit process-algebraic verification techniques to analyze a number of case-studies, including the formal analysis of a single-cycle and a pipelined MIPS processor specified in SystemC.