Model checking
Simulation-guided property checking based on a multi-valued AR-automata
Proceedings of the conference on Design, automation and test in Europe
Verification of embedded systems using a petri net based representation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Functional Verification for SystemC Descriptions Using Constraint Solving
Proceedings of the conference on Design, automation and test in Europe
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
FM '08 Proceedings of the 15th international symposium on Formal Methods
Model checking SystemC designs using timed automata
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Combining Model Checking and Testing in a Continuous HW/SW Co-verification Process
TAP '09 Proceedings of the 3rd International Conference on Tests and Proofs
Shortening the verification cycle with synthesizable abstract models
Proceedings of the 46th Annual Design Automation Conference
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Formal semantics for PSL modeling layer and application to the verification of transactional models
Proceedings of the Conference on Design, Automation and Test in Europe
A framework for verification of software with time and probabilities
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Runtime verification of typical requirements for a space critical SoC patform
FMICS'11 Proceedings of the 16th international conference on Formal methods for industrial critical systems
SystemC waiting state automata
International Journal of Critical Computer-Based Systems
Formal deadlock checking on high-level SystemC designs
Proceedings of the International Conference on Computer-Aided Design
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
Building SystemC waiting state automata
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
A HW/SW co-verification framework for SystemC
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Verifying SystemC using an intermediate verification language and symbolic simulation
Proceedings of the 50th Annual Design Automation Conference
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This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed temporal logic. The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments.