Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Simulation based deadlock analysis for system level designs
Proceedings of the 42nd annual Design Automation Conference
Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Constructing efficient formal models from high-level descriptions using symbolic simulation
International Journal of Parallel Programming
SystemC: From the Ground Up
BTOR: bit-precise modelling of word-level problems for model checking
SMT '08/BPR '08 Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning
Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Petri Nets for Systems Engineering: A Guide to Modeling, Verification, and Applications
Petri Nets for Systems Engineering: A Guide to Modeling, Verification, and Applications
Symbolic model checking on SystemC designs
Proceedings of the 49th Annual Design Automation Conference
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One of the main purposes to use SystemC in system development is to perform system-level verification in the early design stage. However, simulation is still by far the only available solution for the high-level SystemC design verification. Nonetheless, traditional formal verification techniques, which rely on the translation of designs under verification to logic netlists, cannot be easily adopted here due to the concurrent/asynchronous nature and the abundant synthesis flexibilities of the high-level designs. In this paper, we propose a multi-layer modeling to represent the highlevel SystemC designs. By representing the different aspects of the design with different structures --- simulation kernel, predictive synchronization dependence graph (PSDG), and extended Petri net (extPN), our modeling can be very concise and faithfully capture the original design semantics. We develop a formal verification engine on this modeling for the deadlock checks. With various novel ideas to enable the symbolic simulation, bounded model checking (BMC) and invariant checking techniques to work on high-level, our experimental results demonstrate the robustness and effectiveness of the formal deadlock checking on high-level SystemC designs.