Simulation based deadlock analysis for system level designs

Authors:
Xi Chen;Abhijit Davare;Harry Hsieh;Alberto Sangiovanni-Vincentelli;Yosinori Watanabe
Affiliations:
University of California, Riverside, CA;University of California, Berkeley, CA;University of California, Riverside, CA;University of California, Berkeley, CA;Cadence Berkeley Laboratories, Berkeley, CA
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

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Abstract

In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the synchronization dependencies in concurrent systems modeled in the Metropolis design environment, where system functions, high level architectures and function-architecture mappings can be modeled and simulated. We propose a data structure called the dynamic synchronization dependency graph, which captures the runtime (blocking) dependencies. A loop-detection algorithm is then used to detect deadlocks and help designers quickly isolate and identify modeling errors that cause the deadlock problems. We demonstrate our approach through a real world design example, which is a complex functional model for video processing and a high level model of function-architecture mapping.