Modeling and Designing Heterogeneous Systems
Concurrency and Hardware Design, Advances in Petri Nets
Automatic trace analysis for logic of constraints
Proceedings of the 40th annual Design Automation Conference
Utilizing Formal Assertions for System Design of Network Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Assertion-Based Design Exploration of DVS in Network Processor Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Simulation based deadlock analysis for system level designs
Proceedings of the 42nd annual Design Automation Conference
Verifying LOC based functional and performance constraints
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification approach of metropolis design framework for embedded systems
International Journal of Parallel Programming
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We are proposing a formalism to express performance constraints at a high level of abstraction. The formalism allows specifying design performance constraints even before all low level details necessary to evaluate them are known. It is based on a solid mathematical foundation, to remove any ambiguity in its interpretation, and yet it allows quite simple and natural specification of many typical constraints.Once the design details are known, the satisfaction of constraints can be checked either by simulation, or by formal techniques like theorem proving, and, in some cases, by automatic model checking.