Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Automatic trace analysis for logic of constraints
Proceedings of the 40th annual Design Automation Conference
Constraints Specification at Higher Levels of Abstraction
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Verifying LOC based functional and performance constraints
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Survey and taxonomy of IP address lookup algorithms
IEEE Network: The Magazine of Global Internetworking
Assertion-Based Design Exploration of DVS in Network Processor Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Formal Verification Methodology for Checking Data Integrity
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
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System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific designs. To make sure that the executable models behave as they should, the designers often have to "eye-ball" the simulation traces and at best, apply simple "assert" statements orwrite simple trace checkers in some scripting languages. The problem is the lack of a concise and formal method to specify and check desired properties, whether they be functional or performance in nature. In this paper, we apply assertion checking methodology to the system design of network processors. Functional and performance assertions, based on Linear Temporal Logic and Logic of Constraints, are written during the design process. Trace checkers and simulation monitors are automatically generated to validate particular simulationruns or to analyze their performance characteristics. Several categories of assertions are checked throughout the design process, such as equivalence, functionality, transaction, and performance. We demonstrate that the assertion-based methodology is very useful for both system level verification and design exploration.