IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
On the Verification of Temporal Properties
Proceedings of the IFIP TC6/WG6.1 Thirteenth International Symposium on Protocol Specification, Testing and Verification XIII
Constraints Specification at Higher Levels of Abstraction
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Formal verification of embedded system designs at multiple levels of abstraction
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Sequential synthesis using S1S
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utilizing Formal Assertions for System Design of Network Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Assertion-Based Design Exploration of DVS in Network Processor Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verifying LOC based functional and performance constraints
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
System-level performance/power analysis for platform-based design of multimedia applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal analysis of safety-critical system simulations
Proceedings of the 2nd International Conference on Application and Theory of Automation in Command and Control Systems
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Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present algorithms to automatically generate trace checkers from formulas written in the formal quantitative constraint language, Logic Of Constraints (LOC), to analyze the simulation traces for functional and performance constraint violations. For many interesting formulas, the checkers exhibit linear time complexity and constant memory usage. We illustrate the usefulness and efficiency of this approach with large designs and traces.