Assertion-Based Design Exploration of DVS in Network Processor Architectures

Authors:
Jia Yu;Wei Wu;Xi Chen;Harry Hsieh;Jun Yang;Felice Balarin
Affiliations:
University of California, Riverside;University of California, Riverside;University of California, Riverside;University of California, Riverside;University of California, Riverside;Cadence Berkeley Laboratories
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

Citing 6
Cited 2

Design issues for dynamic voltage scaling

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Automatic trace analysis for logic of constraints

Proceedings of the 40th annual Design Automation Conference
Constraints Specification at Higher Levels of Abstraction

HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Utilizing Formal Assertions for System Design of Network Processors

Proceedings of the conference on Design, automation and test in Europe - Volume 3
NePSim: A Network Processor Simulator with a Power Evaluation Framework

IEEE Micro
Verifying LOC based functional and performance constraints

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Power optimization for universal hash function data path using divide-and-concatenate technique

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Assertion-based performance analysis for OCP systems

CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and execution-based DVS, in a network processor model. Using the automatically generated distribution analyzers, we analyze the power and performance distributions and study their trade-offs for the two DVS policies with different parameter settings such as threshold values and window sizes. We discuss the optimal configurations of the two DVS policies under different design requirements. By a set of experiments, we show that the assertion-based trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space.