Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Transaction Based Design: Another Buzzword or the Solution to a Design Problem?
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Assertion-Based Design Exploration of DVS in Network Processor Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SyCE: An Integrated Environment for System Design in SystemC
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Quantitative analysis of transaction level models for the AMBA bus
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The Open Core Protocol (OCP) allows exploring several SoC design architectures to get the final product with better performance, but how to measure the performance is still a problem. In this paper, an assertion-based approach for system-level performance analysis is presented and applied to the single-channel OCP system described with SystemC Transaction Level Models (TLM). In the analysis approach, performance primitives such as data rate and transaction latency are described using the Transaction Level Assertion (TLA), volume of transactions are produced randomly via a generator according to certain probability distribution functions, and performance evaluation results with different OCP configurations are discussed. Our approach is illustrated on a generic Master/Slave architecture from the OCP distribution. The experiment results show that the assertion-based approach can help a designer get the desired configurations with optimal performance in a large design space.