HW/SW co-verification of embedded systems using bounded model checking
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Component-based version management for embedded computing system design
Proceedings of the 2007 ACM symposium on Applied computing
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Assertion-based performance analysis for OCP systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Scoot: a tool for the analysis of SystemC models
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Contribution to graphical representation of SystemC structural model simulation
Proceedings of the 7th FPGAworld Conference
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We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of SystemC designs. The core tools are 1) ParSyC, a parser for SystemC designs that has also some synthesis options, 2) CheckSyC, a verification tool for formal equivalence checking, property checking and generating checkers for simulation or synthesis, 3) DeSyC, a tool for automatic debugging and error location in netlists, and 4) ViSyC, a visualization tool for schematic and source code view supporting crossprobing and annotation of simulation and debugging results. The tools fully support hierarchy and interact tightly. Designs can be described at different levels of abstraction.