Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
System Design with SystemC
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
IPSIM: SystemC 3.0 Enhancements for Communication Refinement
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Fast Exploration of Bus-Based On-Chip Communication Architectures
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
System-level communication modeling for network-on-chip synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Automatic generation of transaction level models for rapid design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Fast and accurate transaction level models using result oriented modeling
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
ACM Transactions on Embedded Computing Systems (TECS)
Assertion-based performance analysis for OCP systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform
Proceedings of the Conference on Design, Automation and Test in Europe
TLM automation for multi-core design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model communication in systems in an abstract manner. Although being widely accepted, TLMs have not been analyzed for their loss in accuracy.This paper will analyze and quantify the speed-accuracy tradeoff of TLM using a case study on AMBA, an industry bus standard. It shows the results of modeling the Advanced High-performance Bus (AHB) of AMBA using a set of models at different abstraction levels. The analysis of the simulation speed shows improvements of two orders of magnitude for each TLM abstraction, while the timing in the model remains accurate for many applications.As a result, the paper will classify the different models towards their applicability in typical modeling situations, allowing the system designer to achieve fast and accurate simulation of communication.