Automatic generation of transaction level models for rapid design space exploration

Authors:
Dongwan Shin;Andreas Gerstlauer;Junyu Peng;Rainer Dömer;Daniel D. Gajski
Affiliations:
University of California, Irvine, CA, USA;University of California, Irvine, CA, USA;University of California, Irvine, CA, USA;University of California, Irvine, CA, USA;University of California, Irvine, CA, USA
Venue:
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Year:
2006

Citing 12
Cited 6

Communication synthesis for distributed embedded systems

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Communication synthesis for distributed embedded systems

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Proceedings of the 38th annual Design Automation Conference
System Design with SystemC

System Design with SystemC
Efficient exploration of the SoC communication architecture design space

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Transaction level modeling: an overview

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS scheduling in transaction level models

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Extending the transaction level modeling approach for fast communication architecture exploration

Proceedings of the 41st annual Design Automation Conference
IPSIM: SystemC 3.0 Enhancements for Communication Refinement

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
System-level automatic model refinement

System-level automatic model refinement
Retargetable generation of TLM bus interfaces for MP-SoC platforms

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Quantitative analysis of transaction level models for the AMBA bus

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Embedded software development on top of transaction-level models

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Flexible and abstract communication and interconnect modeling for MPSoC

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
TLM automation for multi-core design

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A systematic design space exploration approach to customising multi-processor architectures: exemplified using graphics processors

Transactions on High-Performance Embedded Architectures and Compilers IV
Synthesis of optimized hardware transactors from abstract communication specifications

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Quantified Score

Hi-index	0.00

Visualization

Abstract

Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate such transaction-level models from abstract input descriptions. Designers have to write such models manually, which is a tedious and error-prone task, and one of bottlenecks in improving designer's productivity. In this paper, we propose a method to generate transaction-level models from virtual architecture models where components communicate via abstract message-passing channels. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness and benefits of our approach for rapid, early exploration of communication design space.