RTOS scheduling in transaction level models

Authors:
Haobo Yu;Andreas Gerstlauer;Daniel Gajski
Affiliations:
University of California, Irvine, Irvine, CA;University of California, Irvine, Irvine, CA;University of California, Irvine, Irvine, CA
Venue:
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Year:
2003

Citing 6
Cited 8

Operating system based software generation for systems-on-chip

Proceedings of the 37th Annual Design Automation Conference
Task generation and compile-time scheduling for mixed data-control embedded software

Proceedings of the 37th Annual Design Automation Conference
Automatic generation and targeting of application specific operating systems and embedded systems software

Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC

System Design with SystemC
System-level abstraction semantics

Proceedings of the 15th international symposium on System Synthesis
RTOS Modeling for System Level Design

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Heterogeneous MP-SoC: the solution to energy-efficient signal processing

Proceedings of the 41st annual Design Automation Conference
Automatic generation of transaction level models for rapid design space exploration

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Interrupt modeling for efficient high-level scheduler design space exploration

ACM Transactions on Design Automation of Electronic Systems (TODAES)
SciSim: a software performance estimation framework using source code instrumentation

WOSP '08 Proceedings of the 7th international workshop on Software and performance
Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Automatic instrumentation of embedded software for high level hardware/software co-simulation

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Performance- and economisation-oriented scheduling techniques for managing applications with QoS demands in grids

International Journal of Ad Hoc and Ubiquitous Computing
TLM+ modeling of embedded HW/SW systems

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Raising the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impact on system performance, it's much desired that the designer can select the right scheduling algorithm at high abstraction levels so as to save him from the error-prone and time consuming task of tuning code delays or task priority assignments at the final stage of system design. In this paper we tackle this problem by introducing a RTOS model and an approach to refine any unscheduled transaction level model (TLM) to a TLM with RTOS scheduling support. The refinement process provides a useful tool to the system designer to quickly evaluate different dynamic scheduling algorithms and make the optimal choice at the early stage of system design.