A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Virtual synchronization for fast distributed cosimulation of dataflow task graphs
Proceedings of the 15th international symposium on System Synthesis
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS scheduling in transaction level models
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Generic RTOS Model for Real-time Systems Simulation with SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A timing-accurate HW/SW co-simulation of an ISS with SystemC
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS-centric hardware/software cosimulator for embedded system design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fine-grained application source code profiling for ASIP design
Proceedings of the 42nd annual Design Automation Conference
Trace-driven HW/SW cosimulation using virtual synchronization technique
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Scheduling refinement in abstract RTOS models
ACM Transactions on Embedded Computing Systems (TECS)
An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar
AINAW '07 Proceedings of the 21st International Conference on Advanced Information Networking and Applications Workshops - Volume 01
Modeling RTOS for Reactive Embedded Systems
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Cycle-approximate retargetable performance estimation at the transaction level
Proceedings of the conference on Design, automation and test in Europe
Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using a dataflow abstracted virtual prototype for HdS-design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A high-level virtual platform for early MPSoC software development
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Framework for performance analysis of RTOS-enabled embedded systems on FPGA
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
TLM+ modeling of embedded HW/SW systems
Proceedings of the Conference on Design, Automation and Test in Europe
Platform modeling for exploration and synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
GALS-Designer: A design framework for GALS software systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HdSC: a fast and preemptive modeling for on host HdS development
Proceedings of the 24th symposium on Integrated circuits and systems design
Automated, retargetable back-annotation for host compiled performance and power modeling
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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Instruction set simulation and real time operating system modeling have become important issues for the design of distributed embedded systems. This paper presents a holistic approach to simulate a distributed, embedded system that includes target software, processing units, and abstract RTOS within a virtual prototype environment. The processing unit is modeled by an ISS, which is embedded in a SystemC environment to allow the integration into a platform model. In comparison to existing approaches, the RTOS is not directly running on the ISS but outsourced and replaced by an RTOS model. This step strongly reduces simulation time since the execution on the ISS is much more time consuming in contrast to the execution on the host processor. The results show the theoretical and measured performance gain depending on the RTOS scheduler and task switching.