EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Customized instruction-sets for embedded processors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Guest Editors' Introduction: Application-Specific Microprocessors
IEEE Design & Test
Trace-Driven Memory Simulation: A Survey
Performance Evaluation: Origins and Directions
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Profiling tools for hardware/software partitioning of embedded applications
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
High-level algorithmic complexity evaluation for system design
Journal of Systems Architecture: the EUROMICRO Journal
Automatic generation of application specific processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Retargetable profiling for rapid, early system-level design space exploration
Proceedings of the 41st annual Design Automation Conference
ASIP architecture exploration for efficient IPSec encryption: A case study
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Fast compiler optimisation evaluation using code-feature based performance prediction
Proceedings of the 4th international conference on Computing frontiers
Journal of VLSI Signal Processing Systems
Design space exploration of partially re-configurable embedded processors
Proceedings of the conference on Design, automation and test in Europe
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A code-generator generator for multi-output instructions
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A fast and generic hybrid simulation approach using C virtual machine
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Multiprocessor performance estimation using hybrid simulation
Proceedings of the 45th annual Design Automation Conference
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Fast data-cache modeling for native co-simulation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fast cache simulation for host-compiled simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
Loop acceleration exploration for ASIP architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Languages (ADLs) and retargetable software development tools. However, for improved design efficiency, additional pre-architecture exploration tools are required to help narrow-down the huge design space and making coarsegrained Instruction Set Architecture (ISA) decisions before detailed ADL modeling. Extensive application code profiling is the key in such early design stages. Based on a novel code instrumentation technology, we present a microprofiling approach that fills the current gap between source-level and instruction-level profilers and combines their advantages w.r.t. speed and accuracy. We show how the microprofiler is embedded into an advanced ASIP design flow and justify its use in a case study to design an MP3 decoder ASIP.