Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Cycle and phase accurate DSP modeling and integration for HW/SW co-verification
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior
IEEE Transactions on Computers
High level cache simulation for heterogeneous multiprocessors
Proceedings of the 41st annual Design Automation Conference
Fine-grained application source code profiling for ASIP design
Proceedings of the 42nd annual Design Automation Conference
Cache characterization surfaces and predicting workload miss rates
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems
ESTMED '06 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
Automatic instrumentation of embedded software for high level hardware/software co-simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Exact and fast L1 cache simulation for embedded systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Fast instruction cache modeling for approximate timed HW/SW co-simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast cache simulation for host-compiled simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid source-level simulation of data caches using abstract cache models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Efficient design of large multiprocessor embedded systems requires fast, early performance modeling techniques. Native co-simulation has been proposed as a fast solution for evaluating systems in early design steps. Annotated SW execution can be performed in conjunction with a virtual model of the HW platform to generate a complete system simulation. To obtain sufficiently accurate performance estimations, the effect of all the system components, as processor caches, must be considered. ISS-based cache models slow down the simulation speed, greatly reducing the efficiency of native-based co-simulations. To solve the problem, cache modeling techniques for fast native co-simulation have been proposed, but only considering instruction-caches. In this paper, a fast technique for datacache modeling is presented, together with the instrumentation required for its application in native execution. The model allows the designer to obtain cache hit/miss rate estimations with a speed-up of two orders of magnitude with respect to ISS. Miss rate estimation error remains below 5% for representative examples.