DAC '96 Proceedings of the 33rd annual Design Automation Conference
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hybrid simulation for embedded software energy estimation
Proceedings of the 42nd annual Design Automation Conference
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
ISS-centric modular HW/SW co-simulation
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Calibration of abstract performance models for system-level design space exploration
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Cycle-approximate retargetable performance estimation at the transaction level
Proceedings of the conference on Design, automation and test in Europe
Source-level timing annotation and simulation for a heterogeneous multiprocessor
Proceedings of the conference on Design, automation and test in Europe
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An efficient approach for system-level timing simulation of compiler-optimized embedded software
Proceedings of the 46th Annual Design Automation Conference
Fast data-cache modeling for native co-simulation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fast and accurate source-level simulation of software timing considering complex code optimizations
Proceedings of the 48th Design Automation Conference
A universal technique for fast and flexible instruction-set architecture simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate cache modeling in source-level simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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Source-Level Simulation (SLS) has become a de-facto standard technique for fast simulation of embedded software. The basic idea of SLS is to generate software simulation models by annotating low-level timing information into application source code. The obtained source-level simulation models provide a good alternative to traditional Instruction Set Simulators (ISS) for system-level design space exploration of complex embedded systems. However, the generation of source-level simulation models requires the source code to be available, and therefore, it is not applicable to software that contains target dependent code (e.g. inline assembler and pre-compiled library functions). Since target dependent code is often used in embedded software development, this problem strongly limits the applicability of SLS. To overcome this limitation, we propose for the first time a novel hybrid compiled simulation approach called HyCoS that takes advantage of SLS and provides support for target dependent code by incorporating an instruction-level compiled simulation technique. A major challenge to be addressed in the hybrid simulation is the implementation of synchronization and communication between code simulated at different abstraction levels, in order to achieve functional correctness. In addition, it is also crucial to improve estimation accuracy. In this paper we present novel methods for these goals. Experimental results show that, compared to an ISS, HyCoS achieves an average simulation speed of 464 MIPS on a normal desktop computer, 128.0x faster than a standard ISS while achieving comparable accuracy. Even in comparison to fast instruction-level compiled simulation, it also achieves a speedup of up to 4.2x. We also use a multimedia application to demonstrate the efficiency of our approach that is especially beneficial in complex multiprocessor simulation.