Source-level timing annotation and simulation for a heterogeneous multiprocessor

  • Authors:

  • Trevor Meyerowitz;Alberto Sangiovanni-Vincentelli;Mirko Sauermann;Dominik Langen

  • Affiliations:

  • University of California at Berkeley, Berkeley, California;University of California at Berkeley, Berkeley, California;Infineon Technologies, Munich, Germany;Infineon Technologies, Munich, Germany

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2008

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Abstract

A generic and retargetable tool flow is presented that enables the export of timing data from software running on a cycle-accurate Virtual Prototype (VP) to a concurrent functional simulator. First, an annotation framework takes information gathered from running an application on the VP and automatically annotates the line-level delays back to the original source code. Then, a SystemC-based timed functional simulator runs the annotated source code much faster than the VP while preserving timing accuracy. This simulator is API-compatible with the multiprocessor's operating system. Therefore, it can compile and run unmodified applications on the host PC. This flow has been implemented for MuSIC (Multiple SIMD Cores) [6], a heterogeneous multiprocessor developed at Infineon to support Software Defined Radio (SDR). When compared with an optimized cycle-accurate VP of MuSIC on a variety of tests, including a multiprocessor JPEG encoder, the accuracy is within 20%, with speedups from 10x to 1000x.