DAC '96 Proceedings of the 33rd annual Design Automation Conference
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
Timed compiled-code simulation of embedded software for performance analysis of SOC design
Proceedings of the 39th annual Design Automation Conference
ISS-centric modular HW/SW co-simulation
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and Implementation of aWorkload Specific Simulator
ANSS '06 Proceedings of the 39th annual Symposium on Simulation
SciSim: a software performance estimation framework using source code instrumentation
WOSP '08 Proceedings of the 7th international workshop on Software and performance
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Source-level timing annotation and simulation for a heterogeneous multiprocessor
Proceedings of the conference on Design, automation and test in Europe
Framework for fast and accurate performance simulation of multiprocessor systems
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
SysCOLA: a framework for co-development of automotive software and system platform
Proceedings of the 46th Annual Design Automation Conference
RTOS-aware refinement for TLM2.0-based HW/SW designs
Proceedings of the Conference on Design, Automation and Test in Europe
Fast and accurate source-level simulation of software timing considering complex code optimizations
Proceedings of the 48th Design Automation Conference
Dominator homomorphism based code matching for source-level simulation of embedded software
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast and accurate cache modeling in source-level simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid prototyping of multicore embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid source-level simulation of data caches using abstract cache models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Accurate source-level simulation of embedded software with respect to compiler optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 8th ACM workshop on Performance monitoring and measurement of heterogeneous wireless and wired networks
Automated, retargetable back-annotation for host compiled performance and power modeling
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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Software accounts for more than 80% of embedded system development efforts, so software performance estimation is a very important issue in system design. Recently, source level simulation (SLS) has become a state-of-the-art approach for software simulation in system level design. However, the simulation accuracy relies on the mapping between source code and binary code, which can be destroyed by compiler optimizations. This drawback strongly limits the usability of this technique in practical system design. We introduce an approach to overcome this limitation by converting source code to a low level representation, called intermediate source code (ISC). ISC has accounted for most compiler optimizations and has a structure close to binary code, so it allows for accurate back-annotation of timing information from the binary level. To show the benefits of our approach, we present a quantitative comparison of the related techniques with the proposed one, using a set of benchmarks.