STATEMATE: A Working Environment for the Development of Complex Reactive Systems
IEEE Transactions on Software Engineering
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Operating system based software generation for systems-on-chip
Proceedings of the 37th Annual Design Automation Conference
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
System-Level Performance Analysis in SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 41st annual Design Automation Conference
Embedded software generation from system level design languages
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Systemic Embedded Software Generation from SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
RTOS-Centric Hardware/Software Cosimulator for Embedded System Design
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Timed HW-SW cosimulation using native execution of OS and application SW
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
ISS-centric modular HW/SW co-simulation
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A SystemC Refinement Methodology for Embedded Software
IEEE Design & Test
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
A smooth refinement flow for co-designing HW and SW threads
Proceedings of the conference on Design, automation and test in Europe
Cycle-approximate retargetable performance estimation at the transaction level
Proceedings of the conference on Design, automation and test in Europe
Hardware-dependent software synthesis for many-core embedded systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Automatic instrumentation of embedded software for high level hardware/software co-simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An efficient approach for system-level timing simulation of compiler-optimized embedded software
Proceedings of the 46th Annual Design Automation Conference
Correct-by-construction generation of device drivers based on RTL testbenches
Proceedings of the Conference on Design, Automation and Test in Europe
Increased accuracy through noise injection in abstract RTOS simulation
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.