A compilation-based software estimation scheme for hardware/software co-simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Source-level execution time estimation of C programs
Proceedings of the ninth international symposium on Hardware/software codesign
Timed compiled-code simulation of embedded software for performance analysis of SOC design
Proceedings of the 39th annual Design Automation Conference
Architecture-level performance evaluation of component-based embedded systems
Proceedings of the 40th annual Design Automation Conference
Retargetable profiling for rapid, early system-level design space exploration
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Introducing preemptive scheduling in abstract RTOS models using result oriented modeling
Proceedings of the conference on Design, automation and test in Europe
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Automatic instrumentation of embedded software for high level hardware/software co-simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An effective synchronization approach for fast and accurate multi-core instruction-set simulation
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
RTOS-aware refinement for TLM2.0-based HW/SW designs
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate timed RTOS model for transaction level modeling
Proceedings of the Conference on Design, Automation and Test in Europe
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Test exploration and validation using transaction level models
Proceedings of the Conference on Design, Automation and Test in Europe
Increased accuracy through noise injection in abstract RTOS simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Performance modeling of embedded applications with zero architectural knowledge
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A flexible hybrid simulation platform targeting multiple configurable processors SoC
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Source-level timing annotation for fast and accurate TLM computation model generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An Extended SystemC Framework for Efficient HW/SW Co-Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast and accurate cache modeling in source-level simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
Fast cache simulation for host-compiled simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid prototyping of multicore embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic generation of functional models for embedded processor extensions
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Accurate source-level simulation of embedded software with respect to compiler optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Automated, retargetable back-annotation for host compiled performance and power modeling
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multi-core designs. The inputs are application C processes and their mapping to processing units in the platform. The processing unit model consists of pipelined datapath, memory hierarchy and branch delay model. Using the processing unit model, the basic blocks in the C processes are analyzed and annotated with estimated delays. This is followed by a code generation phase where delay-annotated C code is generated and linked with a SystemC wrapper consisting of inter-process communication channels. The generated TLM is compiled and executed natively on the host machine. Our key contribution is that the estimation technique is close to cycle-accurate, it can be applied to any multi-core platform and it produces high-speed native compiled TLMs. For experiments, timed TLMs for industrial scale designs such as MP3 decoder were automatically generated for 4 heterogeneous multi-processor platforms with up to 5 PEs under 1 minute. Each TLM simulated under 1 second, compared to 3--4 hrs of instruction set simulation (ISS) and 15--18 hrs of RTL simulation. Comparison to on-board measurement showed only 8% error on average in estimated number of cycles.