Combined system synthesis and communication architecture exploration for MPSoCs

Authors:
Martin Lukasiewycz;Martin Streubühr;Michael Glaß;Christian Haubelt;Jürgen Teich
Affiliations:
University of Erlangen-Nuremberg, Germany;University of Erlangen-Nuremberg, Germany;University of Erlangen-Nuremberg, Germany;University of Erlangen-Nuremberg, Germany;University of Erlangen-Nuremberg, Germany
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2009

Citing 15
Cited 10

System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures

ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Transaction level modeling: an overview

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Extending the transaction level modeling approach for fast communication architecture exploration

Proceedings of the 41st annual Design Automation Conference
Using TLM for Exploring Bus-based SoC Communication Architectures

ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Task-accurate performance modeling in SystemC for real-time multi-processor architectures

Proceedings of the conference on Design, automation and test in Europe: Proceedings
TLM/network design space exploration for networked embedded systems

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Simulink-based MPSoC design flow: case study of Motion-JPEG and H.264

Proceedings of the 44th annual Design Automation Conference
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
High-performance timing simulation of embedded software

Proceedings of the 45th annual Design Automation Conference
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models

Proceedings of the 45th annual Design Automation Conference
Specify-explore-refine (SER): from specification to implementation

Proceedings of the 45th annual Design Automation Conference
Concurrent topology and routing optimization in automotive network integration

Proceedings of the 45th annual Design Automation Conference
Cycle-approximate retargetable performance estimation at the transaction level

Proceedings of the conference on Design, automation and test in Europe

Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation

Proceedings of the 12th annual conference on Genetic and evolutionary computation
Towards scalable system-level reliability analysis

Proceedings of the 47th Design Automation Conference
Robust design of embedded systems

Proceedings of the Conference on Design, Automation and Test in Europe
PM-COSYN: PE and memory co-synthesis for MPSoCs

Proceedings of the Conference on Design, Automation and Test in Europe
Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Symbolic design space exploration for multi-mode reconfigurable systems

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Symbolic system level reliability analysis

Proceedings of the International Conference on Computer-Aided Design
Considering diagnosis functionality during automatic system-level design of automotive networks

Proceedings of the 49th Annual Design Automation Conference
Concurrent architecture and schedule optimization of time-triggered automotive systems

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IVaM: implicit variant modeling and management for automotive embedded systems

Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of a system. Given an application model written in SystemC TLM 2.0, the proposed approach performs a fully automatic optimization by a simultaneous resource allocation, task binding, data mapping, and transaction routing for MPSoC platforms. To cope with the huge complexity of the design space, a transformation of the transaction level model to a graph-based model and symbolic representation that allows multi-objective optimization is presented. Results from optimizing a Motion-JPEG decoder illustrate the effectiveness of the proposed approach.