The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proceedings of the 6th international workshop on Hardware/software codesign
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comparison of list schedules for parallel processing systems
Communications of the ACM
Proceedings of the conference on Design, automation and test in Europe - Volume 1
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Application mapping for chip multiprocessors
Proceedings of the 45th annual Design Automation Conference
Memory-aware NoC exploration and design
Proceedings of the conference on Design, automation and test in Europe
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
Proceedings of the 36th annual international symposium on Computer architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
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Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory bottleneck. Therefore, to maximize system performance, it is important to simultaneously consider the PE and on-chip memory architecture design. However, in a traditional MPSoC design flow, PE allocation and on-chip memory allocation are often considered independently. To tackle this problem, we propose the first PE and Memory Co-synthesis (PM-COSYN) framework for MPSoCs. One critical issue in such a memory-aware MPSoC design is how to utilize the available die area to achieve a balanced design between memory and computation subsystems. Therefore, the goal of PM-COSYN is to allocate PE and on-chip memory for MPSoCs with Network-on-Chip (NoC) architecture such that system performance is maximized and the area constraint is met. The experimental results show that, PM-COSYN can synthesize NoC resource allocation according to the needs of the target task set. When comparing to a Simulated-Annealing method, PM-COSYN generates a comparable solution with much shorter CPU time.