The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 6th international workshop on Hardware/software codesign
A comparison of list schedules for parallel processing systems
Communications of the ACM
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Introduction to Algorithms
IEEE Transactions on Parallel and Distributed Systems
Strength and Weaknesses of Genetic List Scheduling for Heterogeneous Systems
ACSD '01 Proceedings of the Second International Conference on Application of Concurrency to System Design
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An architectural co-synthesis algorithm for energy-aware network-on-chip design
Proceedings of the 2007 ACM symposium on Applied computing
PM-COSYN: PE and memory co-synthesis for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Process scheduling for future multicore processors
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
A minimal average accessing time scheduler for multicore processors
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
Exploration of heuristic scheduling algorithms for 3D multicore processors
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
A greedy heuristic approximation scheduling algorithm for 3d multicore processors
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing
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Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of System-on-Chip (SoC) design in deep sub-micron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of Processing Elements (PEs) with multiple types and their topology. The software architecture contains allocating tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have concentrated on solving only one or two design parameters at a time. In this paper, we propose a hardware-software co-synthesis algorithm for a heterogeneous NoC architecture. The design goal is to minimize energy consumption while meeting the real-time requirements commonly seen in embedded applications. The proposed algorithm is based on Simulated-Annealing (SA). To compare the solution quality and efficiency of the proposed algorithm, we also implement the branch-and-bound and iterative algorithm to solve the hardware-software co-synthesis problem of a heterogeneous NoC. With the given synthetic task sets, the experimental results show that the proposed SA-based algorithm achieves near-optimal solution in a reasonable time, while the branch-and-bound algorithm takes a very long time to find the optimal solution, and the iterative algorithm fails to achieve good solution quality. When applying the co-synthesis algorithms to a real-world application with PE library that has little variation in PE performance and energy consumption, the iterative algorithm achieves solution quality comparable to that of the proposed SA-based algorithm.