Process scheduling for future multicore processors

Authors:
Thomas Canhao Xu;Pasi Liljeberg;Hannu Tenhunen
Affiliations:
Turku Center for Computer Science (TUCS), Turku, Finland;University of Turku, Turku, Finland;University of Turku, Turku, Finland
Venue:
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Year:
2011

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Abstract

In this paper, we study and analyze process scheduling problems for future multicore processors. It is expected that hundreds or even thousands of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). However, operating system process scheduling, one of the most important design issues for CMP systems, has not been well addressed. We define a model for future CMPs, based on which a scheduling algorithm is proposed to reduce on-chip communication latencies and improve performance. The impact of memory access and inter process communication (IPC) in scheduling are analyzed. We explore six typical core allocation strategies. Results show that, a strategy with a balanced consideration of both IPC and memory access out-performs other strategies, the two metrics (misses per thousand instructions and cache hit latencies) are reduced up to 25.97% and 13.11%, respectively.