FFTs in external or hierarchical memory
The Journal of Supercomputing
The performance of multiprogrammed multiprocessor scheduling algorithms
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
A comparison of sorting algorithms for the connection machine CM-2
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
The SGI Origin: a ccNUMA highly scalable server
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Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Route packets, not wires: on-chip inteconnection networks
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IEEE Transactions on Parallel and Distributed Systems
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
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Dynamic Critical Path Scheduling Parallel Programs onto Multiprocessors
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 8 - Volume 09
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
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ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors
Proceedings of the 13th international symposium on Low power electronics and design
Operating System Concepts
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Proceedings of the 17th international conference on Parallel architectures and compilation techniques
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Journal of Systems Architecture: the EUROMICRO Journal
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CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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In this paper, we explore heuristic scheduling algorithms for future multicore processors. It is expected that hundreds or even thousands of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). To reduce on-chip communication delay and improve efficiency, three-dimensional (3D) integration with Through Silicon Vias (TSVs) is introduced to replace the traditional two-dimensional (2D) implementation. Multiple functional layers can be stacked in 3D CMPs. However, operating system process scheduling has not been well addressed for such systems. We define a model for 3D CMPs, and propose a heuristic scheduling algorithm which aims to reduce cache access latencies and the delay of inter process communication. We explore different scheduling methods and discuss the advantages and disadvantages of our algorithm. Experimental results show that under three different workloads, the execution times of our scheduling method in two configurations are reduced by 14.5% and 5.86% respectively, compared with the other scheduling methods. Two scheduling methods from different heuristics for 8-thread tasks are also compared. This research provides a guideline for designing scheduling algorithms for future 3D CMPs.