An architectural co-synthesis algorithm for energy-aware network-on-chip design

Authors:
Wei-Hsuan Hung;Yi-Jung Chen;Chia-Lin Yang;Yen-Sheng Chang;Alan P. Su
Affiliations:
National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;SpringSoft, Inc.
Venue:
Proceedings of the 2007 ACM symposium on Applied computing
Year:
2007

Citing 6
Cited 2

An architectural co-synthesis algorithm for distributed, embedded computing systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A comparison of list schedules for parallel processing systems

Communications of the ACM
Analysis of power consumption on switch fabrics in network routers

Proceedings of the 39th annual Design Automation Conference
Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-aware communication optimization for networks-on-chips with voltage scalable links

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

An architectural co-synthesis algorithm for energy-aware Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal
The era of many-modules SoC: revisiting the NoC mapping problem

Proceedings of the 2nd International Workshop on Network on Chip Architectures

Quantified Score

Hi-index	0.00

Visualization

Abstract

Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of SoC (System-on-Chip) design in deep submicron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of PEs (Processing Elements) with multiple types and their topology. The software architecture contains the allocation of tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have concentrated on solving for only one or two design parameters at a time. In this paper, we propose a hardware-software co-synthesis algorithm for a heterogeneous NoC architecture. The design goal is to minimize energy consumption while meeting the real-time requirements commonly seen in the embedded applications.