A study of permutation crossover operators on the traveling salesman problem
Proceedings of the Second International Conference on Genetic Algorithms on Genetic algorithms and their application
A router architecture for real-time point-to-point networks
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Compiler-directed channel allocation for saving power in on-chip networks
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Area and performance optimization of a generic network-on-chip architecture
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
An architectural co-synthesis algorithm for energy-aware network-on-chip design
Proceedings of the 2007 ACM symposium on Applied computing
Profile-driven energy reduction in network-on-chips
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Energy-aware synthesis of networks-on-chip implemented with voltage islands
Proceedings of the 44th annual Design Automation Conference
The Journal of Supercomputing
Application mapping for chip multiprocessors
Proceedings of the 45th annual Design Automation Conference
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
Communication Based Proactive Link Power Management
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Adapting application execution in CMPs using helper threads
Journal of Parallel and Distributed Computing
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scheduling framework for real-time dependable NoC-based systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems
Microelectronics Journal
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ScatterD: Spatial deployment optimization with hybrid heuristic/evolutionary algorithms
ACM Transactions on Autonomous and Adaptive Systems (TAAS)
Communication based proactive link power management
Transactions on High-Performance Embedded Architectures and Compilers IV
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Intelligent on/off dynamic link management for on-chip networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
| Hi-index | 0.00 |
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28% on average compared with existing techniques.