Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
Artificial Neural Networks: A Tutorial
Computer - Special issue: neural computing: companion issue to Spring 1996 IEEE Computational Science & Engineering
Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low power techniques for address encoding and memory allocation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Artificial Neural Networks
Contents provider-assisted dynamic voltage scaling for low energy multimedia applications
Proceedings of the 2002 international symposium on Low power electronics and design
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Compiler-directed voltage scaling on communication links for reducing power consumption
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reducing NoC energy consumption through compiler-directed channel voltage scaling
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Power saving in regular interconnection networks
Parallel Computing
Intelligent On/Off Link Management for On-chip Networks
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
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Networks-on-chips (NoCs) provide scalable on-chip communication and are expected to be the dominant interconnection architectures in multicore and manycore systems. Power consumption, however, is a major limitation in NoCs today, and researchers have been constantly working on reducing both dynamic and static power. Among the NoC components, links that connect the NoC routers are the most power-hungry components. Several attempts have been made to reduce the link power consumption at both the circuit level and the system level. Most past research efforts have proposed selective on/off link state switching based on system-level information based on link utilization levels. Most of these proposed algorithms focus on a pessimistic and simple static threshold mechanism which determines whether or not a link should be turned on/off. This paper presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status (i.e., expected future utilization link levels), where links are turned off and on via the use of a small and scalable neural network. Simulation results with various synthetic traffic models over various network topologies show that the proposed work can reach up to 13% power savings when compared to a trivial threshold computation, at very low (