On the self-similar nature of Ethernet traffic (extended version)
IEEE/ACM Transactions on Networking (TON)
Wide area traffic: the failure of Poisson modeling
IEEE/ACM Transactions on Networking (TON)
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Traffic analysis for on-chip networks design of multimedia applications
Proceedings of the 39th annual Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Low power system scheduling and synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The Alpha 21364 Network Architecture
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Energy optimization techniques in cluster interconnects
Proceedings of the 2003 international symposium on Low power electronics and design
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Optimal Lexicographic Shaping of Aggregate Streaming Data
IEEE Transactions on Computers
Optimal voltage allocation techniques for dynamically variable voltage processors
ACM Transactions on Embedded Computing Systems (TECS)
Power Saving in Regular Interconnection Networks Built with High-Degree Switches
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
A Holistic Approach to Designing Energy-Efficient Cluster Interconnects
IEEE Transactions on Computers
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Exploiting last idle periods of links for network power management
Proceedings of the 5th ACM international conference on Embedded software
Compiler-directed proactive power management for networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Software-directed power-aware interconnection networks
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Compiler-directed channel allocation for saving power in on-chip networks
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Compiler-directed voltage scaling on communication links for reducing power consumption
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reducing NoC energy consumption through compiler-directed channel voltage scaling
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Scalable Low-Cost QoS Support for Single-chip Switches
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Software-directed power-aware interconnection networks
ACM Transactions on Architecture and Code Optimization (TACO)
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
Profile-driven energy reduction in network-on-chips
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Proceedings of the conference on Design, automation and test in Europe
The Journal of Supercomputing
A New Cost-Effective Technique for QoS Support in Clusters
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Stochastic DVS-based dynamic power management for soft real-time systems
Microprocessors & Microsystems
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Entry control in network-on-chip for memory power reduction
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the 13th international symposium on Low power electronics and design
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
The Journal of Supercomputing
Providing Full QoS with 2 VCs in High-Speed Switches
Information Networking. Towards Ubiquitous Networking and Services
Communication Based Proactive Link Power Management
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Reliability aware NoC router architecture using input channel buffer sharing
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A variable frequency link for a power-aware network-on-chip (NoC)
Integration, the VLSI Journal
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Segment gating for static energy reduction in Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
System-level exploration of run-time clusterization for energy-efficient on-chip communication
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A case for dynamic frequency tuning in on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Power control of high speed network interconnects in data centers
INFOCOM'09 Proceedings of the 28th IEEE international conference on Computer Communications Workshops
FinFET-based power simulator for interconnection networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
HiPC'07 Proceedings of the 14th international conference on High performance computing
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
Communication-aware task assignment algorithm for MPSoC using shared memory
Journal of Systems Architecture: the EUROMICRO Journal
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trace-driven optimization of networks-on-chip configurations
Proceedings of the 47th Design Automation Conference
NTPT: on the end-to-end traffic prediction in the on-chip networks
Proceedings of the 47th Design Automation Conference
Integration of admission, congestion, and peak power control in QoS-aware clusters
Journal of Parallel and Distributed Computing
Power saving in regular interconnection networks
Parallel Computing
Destination-based adaptive routing on 2D mesh networks
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
A monitor interconnect and support subsystem for multicore processors
Proceedings of the Conference on Design, Automation and Test in Europe
A novel 3D layer-multiplexed on-chip network
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Energy aware DAG scheduling on heterogeneous systems
Cluster Computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Dynamic power saving in fat-tree interconnection networks using on/off links
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
DENS: Data Center Energy-Efficient Network-Aware Scheduling
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
A Structural Customization Approach for Low Power Embedded Systems Design
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
RAFT: A router architecture with frequency tuning for on-chip networks
Journal of Parallel and Distributed Computing
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
Reducing Network-on-Chip energy consumption through spatial locality speculation
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
NoC frequency scaling with flexible-pipeline routers
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
E-MiLi: energy-minimizing idle listening in wireless networks
MobiCom '11 Proceedings of the 17th annual international conference on Mobile computing and networking
Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
On the use of multiplanes on a 2D mesh network-on-chip
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
Dynamic evolution of congestion trees: analysis and impact on switch architecture
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
Proceedings of the International Conference on Computer-Aided Design
Cost / performance trade-offs and fairness evaluation of queue mapping policies
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
On the correct sizing on meshes through an effective congestion management strategy
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Making-a-stop: A new bufferless routing algorithm for on-chip network
Journal of Parallel and Distributed Computing
Communication based proactive link power management
Transactions on High-Performance Embedded Architectures and Compilers IV
Reliability-aware platform optimization for 3D chip multi-processors
The Journal of Supercomputing
Distributed sensor data processing for many-cores
Proceedings of the great lakes symposium on VLSI
Intelligent on/off dynamic link management for on-chip networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Exploiting communication and packaging locality for cost-effective large scale networks
Proceedings of the 26th ACM international conference on Supercomputing
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Energy based performance tuning for large scale high performance computing systems
Proceedings of the 2012 Symposium on High Performance Computing
Power-aware fat-tree networks using on/off links
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
DENS: data center energy-efficient network-aware scheduling
Cluster Computing
Experimental analysis of task-based energy consumption in cloud computing systems
Proceedings of the 4th ACM/SPEC International Conference on Performance Engineering
SloMo: downclockingWiFi communication
nsdi'13 Proceedings of the 10th USENIX conference on Networked Systems Design and Implementation
Energy-efficient multicore chip design through cross-layer approach
Proceedings of the Conference on Design, Automation and Test in Europe
Enabling power efficiency through dynamic rerouting on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Designing energy-efficient NoC for real-time embedded systems through slack optimization
Proceedings of the 50th Annual Design Automation Conference
RISO: relaxed network-on-chip isolation for cloud processors
Proceedings of the 50th Annual Design Automation Conference
Randomized partially-minimal routing: near-optimal oblivious routing for 3-D mesh networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic directories: a mechanism for reducing on-chip interconnect power in multicores
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Ordering circuit establishment in multiplane NoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Contextual partitioning for speech recognition
ACM Transactions on Embedded Computing Systems (TECS)
Destination-based congestion awareness for adaptive routing in 2D mesh networks
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Splittable single source-sink routing on CMP grids: a sublinear number of paths suffice
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
A survey on Green communications using Adaptive Link Rate
Cluster Computing
Automated analysis of performance and energy consumption for cloud applications
Proceedings of the 5th ACM/SPEC international conference on Performance engineering
Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs
Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology
| Hi-index | 0.01 |
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnectionnetworks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper, we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3X power savings (4.6X on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.